1. Technical Field
The present invention relates generally to a semiconductor memory and more particularly to a technology for synchronizing timing of a data strobe signal with timing of a clock signal.
2. Related Art
The degree of high integration and the operating speeds of the semiconductor apparatuses, integrated circuits, etc. have continuously improved over time. The semiconductor apparatuses and the integrated circuits operate in synchronization with a periodic pulse signal such as a clock to increase the operational speed and allow efficient internal operations. Most semiconductor apparatuses and integrated circuits operate using an external clock and/or a self-generated internal clock.
In a semiconductor memory apparatus, data are inputted in synchronization with a data strobe signal DQS, and a command signal is inputted in synchronization with a clock signal CLK. When operating a high speed data input/output operations, the timing margin between two DQS and CLK signals is reduced, and it may lead to problems in the data input/output operations, which will be described in more detail with respect to FIGS. 1A-1C.
FIG. 1A-1C are timing diagrams related to an operation when a ‘tccd’ (for example, an internal burst length) is a 4tck (CASE A), 5tck (CASE B), and 6tck (CASE C), respectively.
In the CASE A, (1) the pattern of a preamble of a data strobe signal DQS is recognized, (2) the position of the preamble of the data strobe signal DQS is determined, and (3) a clock signal CLK and the data strobe signal DQS are synchronized to each other. The data then can be inputted for storage in an internal memory block, in response to first and second write commands WT and in synchronization with the data strobe signal DQS, which is internally synchronized with the clock signal CLK.
In the CASE B and CASE C, (1) the pattern of a preamble of a first data strobe signal DQS is recognized, (2) the position of the data strobe signal DQS is determined, and (3) a clock signal CLK and the data strobe signal DQS are synchronized to each other. Data, which is inputted in response to a first write command WT, is processed by the internally synchronized clock signal CLK and the data strobe signal DQS, and is stored in the internal memory block. The pattern of a preamble of a second data strobe signal DQS is recognized, the position of the preamble of the data strobe signal DQS is determined, and the clock signal CLK and the data strobe signal DQS are resynchronized with each other. Data, which is inputted in response to a second write command WT, is processed by the internally resynchronized clock signal CLK and data strobe signal DQS, and is stored in the internal memory block.
As described above, in order to synchronize the clock signal CLK and the data strobe signal DQS, the general semiconductor memory apparatus promises the position of the preamble of the data strobe signal and adjusts the width of the preamble. However, in order to perform the above-mentioned operation, it is necessary for the semiconductor memory apparatus to include an additional preamble detection circuit for detecting position information of the preamble.